AIROC Bluetooth Low Energy 5.4 MCU

The Cortex®-M33 has single-cycle multiply and a memory protection unit (MPU). It can run at up to 96 MHz in LP mode and 48 MHz in ULP mode. This is the main CPU, designed for a short interrupt response time, high code density, and high throughput.

Cortex®-M33 implements a version of the Thumb instruction set based on Thumb-2 technology (defined in the Armv8-M architecture reference manual).

The main MCU also implements device-level security, safety, and protection features. Cortex®-M33 provides a secure, interruptible boot function. This guarantees that post boot, system integrity is checked and memory and peripheral access privileges are enforced.

The CPU has the following power draw, at VDDD = 3.0 V and using the internal buck regulator.

The CPU can be selectively placed in Sleep and Deep Sleep power modes as defined by Arm®. The CPU also implements a Deep Sleep RAM (DS-RAM) mode in which almost all the circuits except RAM are powered OFF. Data in RAM is retained to maintain state. Upon exit, the CPU goes through a reset but can use the data in RAM to skip software initialization.

The CPU also has nested vectored interrupt controllers (NVIC) for rapid and deterministic interrupt response, and wake up interrupt controllers (WIC) for CPU wake up from Deep Sleep power mode.

CYW20829 has a debug access port (DAP) that acts as the interface for device programming and debug. An external programmer or debugger (the “host”) communicates with the DAP through the device serial wire debug (SWD) or Joint Test Action Group (JTAG) interface pins. Through the DAP (and subject to device security restrictions), the host can access the device memory and peripherals as well as the registers in the CPU.

CPU debug and trace features are as follows:

• Six hardware breakpoints and four watchpoints, serial wire viewer (SWV), and printf()-style debugging through the single wire output (SWO) pin

The CPU has interrupt request lines (IRQ), with the interrupt source ‘n’ directly connected to IRQn.

Each interrupt supports eight configurable priority levels. One system interrupt can be mapped to the CPU non-maskable interrupts (NMI). Multiple interrupt sources are capable of waking the device from Deep Sleep power mode using the WIC.

Datawire is a light weight DMA controller with 16 channels, which support CPU-independent accesses to memory and peripherals. The descriptors for the channels are in SRAM and the number of descriptors is limited only by the size of the memory. Each descriptor can transfer data in two nested loops with configurable address increments to the source and destination.

A combination of HW and SW is able to support several cryptographic functions. Specifically it supports the following functions:

• Encryption/decryption
  • AES-128 hardware accelerator with following supported modes:
    • Electronic Code Book (ECB)
    • Cipher Block Chaining (CBC)
    • Cipher Feedback (CFB)
    • Output Feedback (OFB)
    • Counter (CTR)
• Hashing
  • Secure Hash Algorithm (SHA-256) hardware accelerator
• Message Authentication Functions (MAC)
  • Hashed Message Authentication Code (HMAC) acceleration using SHA-256 hardware
• True Random Number Generator (TRNG)
• Vector unit hardware accelerator
  • Digital Signature Verification using RSA
  • Digital Signature Verification using ECDSA

CYW20829 has multiple types of protection to control erroneous or unauthorized access to memory and peripheral registers.

Protection units support memory and peripheral access attributes including address range, read/write, code/data, privilege level, secure/non-secure, and protection context.

Protection units are configured at “Secure Boot” to control access privileges and rights for bus masters and peripherals. Up to eight protection contexts (“Secure Boot” is in protection context 0) allow access privileges for memory and system resources to be set by the “Secure Boot” process per protection context by bus master and code privilege level. Multiple protection contexts are available.

AES-128 component to accelerate block cipher functionality. This functionality supports forward encryption of a single 128 bit block with a 128 bit key. SHA-256 component to accelerate hash functionality. This component supports message schedule calculation for a 512-bit message chunk and processing of a 512-bit message chunk.

VU component to accelerate asymmetric key cryptography (for example, RSA and ECC). This component supports large integer multiplication, addition, and so on. TRNG component based on a set of ring oscillators.

The TRNG includes a HW health monitor.

CYW20829 supports the CAN FD controller that supports one CAN FD channel. All CAN FD controllers are compliant with the ISO 11898-1:2015 standard; an ISO 16845:2015 certificate is available. It also implements the time-triggered CAN (TTCAN) protocol specified in ISO 11898-4 (TTCAN protocol levels 1 and 2) completely in hardware. All functions concerning the handling of messages are implemented by the RX and TX handlers. The RX handler manages message acceptance filtering, transfer of received messages from the CAN core to a message RAM, and provides receive-message status. The TX handler is responsible for the transfer of transmit messages from the message RAM to the CAN core, and provides transmit-message status. CAN FD is only available in CYW20829B0010.

CYW20829 contains a LIN channel. Each channel supports transmission/reception of data following the LIN protocol according to ISO standard 17987. Each LIN channel connects to an external transceiver through a 3-pin interface (including an enable function) and supports master and slave functionality. Each block also supports classic and enhanced checksum, along with break detection during message reception and wake-up signaling. Break detection, sync field, checksum calculations, and error interrupts are handled in hardware. LIN is only available in CYW20829B0010.

• Year/Month/Date, Day-of-week, Hour: Minute: Second fields
• 12 and 24 hour formats
• Automatic leap-year correction

CYW20829 contains the SRAM, ROM, and eFuse memory blocks.

• SRAM: CYW20829 has 256-KB of SRAM. Power control and retention granularity is 64-KB blocks allowing the user to control the amount of memory retained in Deep Sleep. Memory is not retained in Hibernate mode.
• ROM: The 64-KB ROM, also referred to as the supervisory ROM (SROM), provides code (ROM Boot) for several system functions. The ROM contains, primarily device initialization and security. ROM code is executed, in protection context 0.
• eFuse: A one-time programmable (OTP) eFuse array consists of 1024 bits, which are reserved for system use such as Die ID, Device ID, initial trim settings, device life cycle, and security settings. Some of the bits are available for storing security key information and hash values and can be programmed by the user for device security. Each fuse is individually programmed; once programmed (or “blown”), its state cannot be changed. Blowing a fuse transitions it from the default state of ‘0’ to ‘1’. To program an eFuse, VDDIO1 must be at 2.5 V ±5%. Because blowing an eFuse is an irreversible process, programming is recommended only in mass production under controlled factory conditions by Infineon provided provisioning tools.

On a device reset, the boot code in ROM is the first code to execute. This code performs the following:

• Device trim setting (calibration)
• Setting the device protection units
• Setting device access restrictions for secure life cycle states
• Configures the Debug Access Port
• In secure life cycle supports secure debug via authenticated debug token
• Configures the SMIF for external flash access
• In secure life cycle validates first user code in external flash by checking its digital signature. Supports OTF decryption of encrypted images in external flash
• Copies the application bootstrap from the external flash to SRAM and jumps to the ROM. It cannot be changed and acts as the Root of Trust in a secure system

It should also be noted that the ROM code sets the system clock to 48 MHz IHO source.

The 32-bit (4 GB) address space is divided into the regions shown in Table 3. Note that code can be executed from the Code, and Internal RAM or External flash.

The device memory map is shown in Table 3.

CYW20829 can operate in four system and three CPU power modes. These modes are intended to minimize the average power consumption in an application. For more details on power modes and other power-saving configuration options, see the relevant application note.

Power modes supported by CYW20829, in the order of decreasing power consumption, are:

• System Low-power (LP) - All peripherals and CPU power modes are available at maximum speed
• System Ultra Low-power (ULP) - All peripherals and CPU power modes are available, but with limited speed
• CPU Active - CPU is executing code in system LP or ULP mode
• CPU Sleep - CPU code execution is halted in system LP or ULP mode
• CPU Deep Sleep - CPU code execution is halted and system Deep Sleep is requested in system LP or ULP mode
• System Deep Sleep - only low-frequency peripherals are available after both CPUs enter CPU Deep Sleep mode
• System Hibernate - Device and I/O states are frozen and the device resets on wakeup. Multiple sources available to wake up from this mode, including RTC, P0.5 and P1.4
• Deep Sleep RAM - only RAM and IO states are retained. All system activity except for select low power peripherals ceases until system exits from this state. The CPU resets upon exit but can skip software initialization since RAM is retained

CPU Active, Sleep, and Deep Sleep are standard Arm®-defined power modes supported by the Arm® CPU instruction set architecture (ISA). System LP, ULP, Deep Sleep, Deep Sleep RAM and Hibernate modes are additional low-power modes supported by the CYW20829.

CYW20829 clock system consists of a combination of oscillators, external clock, and frequency-locked loop.

Specifically, the following:

• Internal main oscillator (IMO)
• Internal low-speed oscillator (ILO)
• Watch crystal oscillator (WCO)
• System 24 MHz crystal oscillator
• External clock input
• One frequency-locked loop (FLL)
• Internal high-speed oscillator (IHO)

Clocks may be buffered and brought out to a pin on a smart I/O port.

Table 4 shows the mapping of port and associated clock group mapped to peripherals.

The IMO is the primary source of internal clocking. It is trimmed during testing to achieve the specified accuracy.

The IMO default frequency is 8 MHz and tolerance is ±2%.

The ILO is a very low power oscillator, nominally 32 kHz, which operates in all power modes.

The PILO is a precision low-power oscillator running at 32 kHz. It is factory calibrated to meet Bluetooth® Low Energy requirements. Like the ILO, it can operate in all power modes.

CYW20829 uses a 24 MHz crystal oscillator (XTAL).

The XTAL must have an accuracy as defined by the Bluetooth® specification. Two external load capacitors are required to work with the crystal oscillator. The selection of the load capacitors is XTAL-dependent (see Figure 4).

CYW20829 includes a 32 kHz oscillator to provide accurate timing during low power operations. Figure 5 shows the 32 kHz XTAL oscillator with external components and Table 6 lists the oscillator’s characteristics. This oscillator can be operated with a 32 kHz or 32.768 kHz crystal oscillator or be driven with a clock input at similar frequency. The XTAL must have an accuracy of ±250 ppm or better per the Bluetooth® spec over temperature and including aging. The default component values are: C1 = C2 = ~6 pF. The values of C1 and C2 are used to fine-tune the oscillator.

CYW20829 has one WDT and two multi-counter WDTs (MCWDTs). The WDT has a 16-bit free-running counter. Each MCWDT has two 16-bit counters and one 32-bit counter, with multiple operating modes. All of the 16-bit counters can generate a watchdog device reset. All of the counters can generate an interrupt on a match event.

The WDT is clocked by the ILO. It can do interrupt/wakeup generation in system LP/ULP, Deep Sleep, and Hibernate power modes. The MCWDTs are clocked by LFCLK (ILO or WCO). It can do periodic interrupt/wakeup generation in system LP/ULP and Deep Sleep power modes.

Integer and fractional clock dividers are provided for peripheral use and timing purposes. There are one or more:

• 8-bit clock dividers
• 16-bit integer clock dividers
• 16.5-bit fractional clock dividers
• 24.5-bit fractional clock divider

CYW20829 contains a trigger multiplexer block. This is a collection of digital multiplexers and switches that are used for routing trigger signals between peripheral blocks and between GPIOs and peripheral blocks.

There are two types of trigger routing. Trigger multiplexers have reconfigurability in the source and destination. There are also hardwired switches called “one-to-one triggers”, which connect a specific source to a destination. The user can enable or disable the route.

CYW20829 can be reset from a variety of sources:

• Power-on reset (POR) to hold the device in reset while the power supply ramps up to the level required for the device to function properly. POR activates automatically at power-up
• Brown-out detect (BOD) reset to monitor the digital voltage supply VDDD and generate a reset if VDDD falls below the minimum required logic operating voltage
• External reset dedicated pin (XRES) to reset the device using an external source. The XRES pin is active LOW. It can be connected either to a pull-up resistor to VDDD, or to an active drive circuit, as Figure 6 shows. If a pull-up resistor is used, select its value to minimize current draw when the pin is pulled LOW; 10 kΩ is typical

• Watchdog Timer (WDT or MCWDT) to reset the device if firmware fails to service it within a specified timeout period
• Software-initiated reset to reset the device on demand using firmware
• Logic-protection fault can trigger an interrupt or reset the device if unauthorized operating conditions occur; for example, reaching a debug breakpoint while executing privileged code
• Hibernate wakeup reset to bring the device out of the system Hibernate low-power mode

Reset events are asynchronous and guarantee reversion to a known state. Some of the reset sources are recorded in a register, which is retained through reset and allows software to determine the cause of the reset.

The ADC block is a single switched-cap Σ-Δ ADC core for audio and DC measurement. It operates at the 12-MHz clock rate and has eight GPIO inputs. The internal bandgap reference has ±5% accuracy without calibration. Different calibration and digital correction schemes can be applied to reduce ADC absolute error and improve measurement accuracy in DC.

One of three internal references may be used for the ADC reference voltage: VDDA, VDDA/2, and an analog reference (AREF). AREF is nominally 1.2 V, trimmed to ±1%.

• The TCPWM supports the following operational modes:
  • Timer-counter with compare
  • Timer-counter with capture
  • Quadrature decoding
  • Pulse width modulation (PWM)
  • Pseudo-random PWM
  • PWM with dead time
• Up, down, and up/down counting modes
• Clock pre-scaling (division by 1, 2, 4,....64, 128)
• Double buffering of compare/capture and period values• Underflow, overflow, and capture/compare output signals
• Supports interrupt on:
  • Terminal count - Depends on the mode; typically occurs on overflow or underflow
  • Capture/compare - The count is captured to the capture register or the counter value equals the value in the compare register
• Complementary output for PWMs
• Selectable start, reload, stop, count, and capture event signals for each TCPWM; with rising edge, falling edge, both edges, and level trigger options. The TCPWM has a Kill input to force outputs to a predetermined state.

In this device there are:

• Two 32-bit TCPWMs
• Seven 16-bit TCPWMs

• This product line has three SCBs:
  • First SCB: Configurable as SPI or I²C
  • Second SCB: Configurable as SPI or UART
  • Third SCB: Configurable as I²C or UART
• One SCB (SCB #0) can operate in system Deep Sleep mode with an external clock; this SCB can be either SPI slave or I²C slave
• I²C mode: The SCB can implement a full multi-master and slave interface (it is capable of multimaster arbitration). This block can operate at speeds of up to 1 Mbps (Fast Mode Plus). It also supports EZI2C, which creates a mailbox address range and effectively reduces I²C communication to reading from and writing to an array in the memory. The SCB supports a 256-byte FIFO for receive and transmit. The I²C peripheral is compatible with I²C standard-mode, Fast Mode, and Fast Mode Plus devices. The I²C bus I/O is implemented with GPIO in open-drain modes.

• UART mode: This is a full-feature UART operating at up to 8 Mbps. It supports automotive single-wire interface (LIN) (only available for CYW20829B0010), infrared interface (IrDA), and SmartCard (ISO 7816) protocols, all of which are minor variants of the basic UART protocol. In addition, it supports the 9-bit multiprocessor mode that allows the addressing of peripherals connected over common Rx and Tx lines. Common UART functions such as parity error, break detect, and frame error are supported. A 256-byte FIFO allows much greater CPU service latencies to be tolerated
• SPI mode: The SPI mode supports full SPI, Secure Simple Pairing (SSP) (essentially adds a start pulse that is used to synchronize SPI Codecs), and Microwire (half-duplex form of SPI). The SPI block supports an EZSPI mode in which the data interchange is reduced to reading and writing an array in memory. The SPI interface operates with a 24-MHz clock

A serial memory interface is provided, running at up to 48 MHz. It supports single, dual and quad SPI configurations, and supports up to four external memory devices. It supports two modes of operation:

• Memory-mapped I/O (MMIO), a command mode interface that provides data access via the SMIF registers and FIFOs
• Execute-in-Place (XIP), in which AHB reads and writes are directly translated to SPI read and write transfers

In XIP mode, the external memory is mapped into the CYW20829 internal address space, enabling code execution directly from the external memory. To improve performance, a 32 KB cache is included. XIP mode also supports AES-128 based on-the-fly encryption and decryption, enabling secure storage and access of code and data in the external memory.

The audio subsystem is only available in CYW20829B0010, it consists of the following hardware blocks:

• One inter-IC sound (I²S) interface
• Two pulse-density modulation (PDM) to pulse-code modulation (PCM) decoder channels

The I²S interface implements two independent hardware FIFO buffers - TX and RX, which can operate in master or slave mode. The following features are supported:

• Multiple data formats - I²S, left-justified, Time Division Multiplexed (TDM) mode A, and TDM mode B
• Programmable channel/word lengths - 8/16/18/20/24/32 bits
• Internal/external clock operation. Up to 192 ksps
• Interrupt mask events - trigger, not empty, full, overflow, underflow, watchdog
• Configurable FIFO trigger level with datawire support

The I²S interface is commonly used to connect with audio codecs, simple DACs, and digital microphones. The PDM-to-PCM decoder implements a single hardware Rx FIFO that decodes a stereo or mono 1-bit PDM input stream to PCM data output. The following features are supported:

• Programmable data output word length - 16/18/20/24 bits
• Configurable PDM clock generation. Range from 384 kHz to 3.072 MHz
• Droop correction and configurable decimation rate for sampling; up to 48 ksps
• Programmable high-pass filter gain
• Interrupt mask events - not empty, overflow, trigger, underflow
• Configurable FIFO trigger level with DMA support

The PDM-to-PCM decoder is commonly used to connect to digital PDM microphones. Up to two microphones can be connected to the same PDM data line.