PSoC™ 6 CAD, BSDL, and IBIS files
CAD, BDSL, and IBIS files can be used in various tools to help engineers design, test, and debug devices that integrate PSoC™ 6 products.
PSoC™ 6 CAD Library Files
PSoC™ 6 CAD libraries provide footprint and schematic support for common PCB design software like Allegro, Altium. CAD libraries for the various product families are listed in the table below.
PSoC™ 6 Product Family | CAD Library File |
|---|---|
CY8C61x4, CY8C62x4 | |
CY8C61x5, CY8C62x5, CYB064x5 | |
CY8C61x6, CY8C61x7, CY8C62x6, CY8C62x7, CYB064x7 | |
CY8C61x8, CY8C61xA, CY8C62x8, CY8C62xA, CYB064xA, CYS064xA |
PSoC™ 6 BSDL Files
Boundary-Scan Description Language (BSDL) is a subset of VHDL (VHSIC Hardware Description Language) that describes how boundary-scan (JTAG) is implemented in a device and how the device operates. It defines the data transport characteristics of the device, how it captures, shifts, and updates scanned data. Boundary-scan tools usually require that the user supply BSDL files for the devices being used in order to properly generate test vectors and perform in-system programming and functional testing.
PSoC™ 6 BSDL files for the various product families are listed in the below table.
PSoC™ 6 Product Family | BSDL File |
|---|---|
CY8C61x4, CY8C62x4 | |
CY8C61x5, CY8C62x5, CYB064x5 | |
CY8C61x6, CY8C61x7, CY8C62x6, CY8C62x7, CYB064x7 | |
CY8C61x8, CY8C61xA, CY8C62x8, CY8C62xA, CYB064xA, CYS064xA |
PSoC™ 6 IBIS Files
“Input/Output (I/O) Buffer Information Specification” (IBIS) is a text file that contains electrical characteristics of a device. The type of information provided in the file is useful for PC-board design where signal integrity and timing analysis is done to design a part into a system.
PSoC™ 6 IBIS files for the various product families are listed in the below table.
PSoC™ 6 Product Family | IBIS File |
|---|---|
CY8C61x4, CY8C62x4 | |
CY8C61x5, CY8C62x5, CYB064x5 | |
CY8C61x6, CY8C61x7, CY8C62x6, CY8C62x7, CYB064x7 | |
CY8C61x8, CY8C61xA, CY8C62x8, CY8C62xA, CYB064xA, CYS064xA |