AN230371 High voltage subsystem (HVSS) in PSOC HV PA family

About this document

Scope and purpose

This application note introduces you to the high-voltage subsystem (HVSS) of PSOC™ 4 HV precision analog (PA) family. This application note also guides you to develop HVSS hardware and firmware design for battery monitoring application.

Intended audience

This document is intended for hardware and firmware design engineers.

Introduction

This application note provides an overview of the high-voltage subsystem (HVSS) with the CY8C41xxLCE-HV4xx series from the PSOC™ 4 high voltage (HV) precision analog (PA) family. PSOC™ 4 HV PA is a fully integrated programmable embedded system for battery monitoring and management. The system features an Arm® Cortex® M0+ processor and programmable and reconfigurable analog and digital blocks. To get a better understanding of the HVSS functionality described and terminology used in this application note, it is a good idea to read the "Section 22: High-voltage subsystem" chapter of the

architecture reference manual

HVSS overview

The PSOC™ 4 HV PA high-voltage subsystem (HVSS) contains a series of analog circuits used in battery monitoring and management applications. The applications are directly connected to an automotive battery and operates up to 42 V. The HVSS has the following features:

HVSS circuits operate directly off 12 V/24 V automotive battery (tolerates up to 42 V)
A linear regulator powered by the automotive battery voltage producing 3.3 V (HVREG)
- Output voltage accuracy: 2.7 V to 3.6 V
- Input voltage range: 3.6 V to 42 V
- Output current capability: 30 mA
- Low current consumption for always on: 20 µA maximum
- Power good function
A LIN physical interface transceiver (LIN PHY)
- Data rates up to 20 kbps with high EM noise immunity
- Positive/negative DC tolerance for LIN pin: –27 V to 42 V
- Sleep mode current consumption: IVBAT + IVDDD = 10 µA maximum
- Programmable slew rate control: 1.0/1.5/2.0 V/us at VBAT = 12 V
- Dominant timeout and LIN wakeup interrupt timers
A set of input voltage dividers (VDIVIDER) providing attenuated signals to ADCs
- Dividers attenuate the input by a factor of 16x or 24x
- 1.2 V full-scale outputs from an input of 19.2 V (16x) or 28.8 V (24x)
An AHB bus interface and control/status registers
Interrupt logic

Figure 1

shows the block diagram for the HVSS.

HV regulator (HVREG)

The HVREG is the high-voltage regulator with self-startup from the battery without a reference voltage; it provides 3.3 V to VDDD and VDDA as the chip supply. It also contains a power good function and Zener diode on the output pin for overvoltage protection. The HVREG operates with stability against automotive battery voltage transient events, keeping the output voltage between 2.7 V to 3.6 V even if the VBAT pin drops down to 3.6 V in cold cranking or rises up to 42 V in a load dump surge.

LIN PHY

The LIN PHY is the interface between the local interconnect network (LIN) protocol controller and the physical bus in a LIN, which meets the requirements of LIN standard 2.2 A and is backward compatible with LIN 2.0. It supports data rates of 1 to 20 kbps. Non-LIN fast slew rates are available providing 100 kbps data rates for fast downloads, for factory and field flash program updates using the LIN pin.

HV ADC voltage dividers (VDIVIDER)

The VDIVIDER is a voltage divider used on the VSENSE and VDIAG pins to scale the battery voltage to levels compatible with on-chip ADCs so that battery voltages can be measured. In typical battery monitoring and management applications, the VSENSE input is normally connected directly to the battery with a series 2.2 kΩ resistor to measure battery voltage. VDIAG can be used to measure the voltage at other locations such as the ECU or other loads where monitoring is desired. The external 2.2 kΩ resistors in series with voltage sources limit the current during ESD and transient voltage events.

HVREG

Block description

Figure 2

shows the HVREG block architecture and function diagram. The HVREG generates a nominal 3.3 V output voltage with loads up to 30 mA from an external supply voltage input of 3.6 V to 42 V. The regulator maintains the output voltage from 3 V to 3.6 V when the supply voltage is greater than 4 V and may drop to 2.7 V when the supply is between 3.6 V to 4 V. In normal operation, the external automotive battery voltage is typically 12 V or higher but can drop as low as 4.5 V during cold cranking. However, the voltage at the V

_BAT

pin can go as low as 3.6 V due to a reverse polarity protection diode and an EMI filter resistor.

This regulator provides 3.3 V

_DDD

(and 3.3 V

_DDA

), which are used to power the chip, including the digital regulators which then generate

_CCD

(1.8 V) supplies. This regulator is always powered on.

Figure 2.
HVREG block architecture and function diagram

HVREG input pins

vddd_in is an analog input signal pin to monitor the

_DDD

voltage level with the power good circuit (PG). This pin is connected to the output

_DDD

at the appropriate place in the chip to monitor the drop in

_DDD

HVREG output pins

vddd is the output pin of this regulator, a nominal 3.3 V regulated voltage with loads up to 30 mA. This output drives the device’s

_DDD

and

_DDA

, and through the GPIO can drive external loads. The vddd pin is always ON after startup.

pg_hv

is the output pin of the power good circuit in HVREG. HVREG monitors the

_DDD

output voltage through the

vddd_in

pin. When

_DDD

is lower than 2 V,

pg_hv

provides a LOW. Thus, this output signal can work as the reset signal of the entire device in the voltage range lower than Vddd = 2.0 V.

Operating voltage

Table 1

and

Table 2

show the HVREG absolute maximum ratings and operating conditions. See

PSOC™ 4 HV PA datasheet

for more information.

Table 1.
HVREG absolute maximum ratings
Parameter	Description	Min.	Typ.	Max.	Units
V _BAT	Supply voltage V _BAT	−0.3	–	42	V
I _BAT	V _BAT supply current	–	–	160	mA
I _BATABSDC	V _BAT supply current, long-term average	–	–	40	mA

Table 2.
HVREG operating conditions
Parameter	Description	Min	Typ	Max	Units	Details/conditions
V _BAT	Battery supply voltage V _BAT	3.6	–	28	V
V _DDA	Analog regulator voltage	3	3.3	3.6	V
I _DDA	Analog regulator current	–	N/A	–	–	Not to be used off-chip
V _DDD	Digital regulator voltage, V _BAT > 4 V	3	3.3	3.6	V
V _DDD	Digital regulator voltage, 4 V≥ V _BAT ≥3.6 V	2.7	–	3.6	V
I _DD	Digital regulator current	–	–	30	mA	Core, GPIO, and external loads

VDIVIDER

Block description

VDIVIDER is used to scale the high-voltage analog inputs down to levels compatible with the ADC full-scale input voltage (1.2 V). These programmable dividers support two voltage scales – 16x (19.2 V full scale) or 24x (28.8 V full scale). Each divider can be independently enabled or disabled. The divider generates a differential signal for the ADC with the bottom of the divider referenced to vdiv_ret.

Figure 3

shows the block diagram of the VDIVIDER.

VDIVIDER input pins

pg_hv

is the reset signal input pin. While this pin is LOW, the level shift circuit is in reset;

vs_div0/vs_div1

outputs "L" regardless of the

rdiv_en<1:0>

voltage level. The voltage level of this bus signals is

_DDD

rdiv_en<1:0>

is an input bus for enabling the resistor dividers of the vsense and

vdiag

inputs. When either signal is set to "L", the corresponding resistor ladder is opened and its output becomes low. The voltage level of this bus signals is

_CCD

rdiv_scale<1:0>

is an input bus to set the voltage attenuator ratio to either 1/16 or 1/24. The voltage level of this bus is

_CCD

VDIVIDER output pins

vs_div0/vs_div1

are output pins of the divided

vsense/vdiag

signals. The voltage level of this bus is

_DDD

Operating voltage

Table 3

and

Table 4

show the VDIVIDER absolute maximum ratings and operating conditions. See

PSOC™ 4 HV PA datasheet

for more information.

Table 3.
VDIVIDER absolute maximum ratings
Parameter	Description	Min.	Typ.	Max.	Units	Details/conditions
V _SHV	V _SENSE /V _DIAG ADC sense voltage	−0.3	–	42	V
V _SHV	V _SENSE /V _DIAG ADC sense voltage	−40	–	42	V	With external 2.2 kΩ resistor
I _SH	V _SENSE /V _DIAG current	−20	–	1	mA	Forced externally

Table 4.
VDIVIDER operating conditions
Parameter	Description	Min.	Typ.	Max.	Units	Details/conditions
V _SENSE	V _BAT sense voltage	3.6	–	28	V
V _DIAG	V _DIAG sense voltage	3.6	–	28	V
I _SENSE	V _SENSE /V _DIAG current		5	20	μA
V _RMEAS	HV measurement range	0	–	28	V	With HVATTEN = 24
V _RMEASLV	LV measurement range	0	–	1.2	V
V _RES	Resolution	–	0.293	–	mV	0 V to 18 V input range (Rdiv=16)
V _RES	Resolution	–	0.4	–	mV	0 V to 28 V input range (Rdiv=24)

LIN PHY

Block description

The LIN driver includes slew control to maintain a consistent duty cycle over a range of loads. It also includes turn-on/turn-off control to round the edges and minimize the EMI. Large amounts of RF energy can be present on the LIN bus; the driver must remain functional in the presence of this energy, which requires special attention to the design of the feedback circuits so they do not saturate in the presence of RF energy.

LIN receiver thresholds are specified in relation to the supply voltage, VBAT. A comparator with voltage dividers sets the receiver threshold and scales the bus voltages to appropriate levels. Noise filtering is needed to prevent the RF energy and brief transients from disturbing the communication.

The LIN specification has certain isolation requirements to ensure that the LIN bus is not compromised by certain faults, and that the loss of supply voltage or the ground of a slave node does not affect the LIN communication between other nodes. To address this requirement, the following are introduced:

Reverse protection diodes in series with pull-up resistors
A diode in series with the open-drain pull-down resistor to prevent powering the components from the LIN bus and/or excessively loading the LIN bus and disrupting the communication

Figure 4

shows the LIN PHY transceiver block diagram.

LIN PHY input pins


Pin	Description
`lin_mode<2:0>`	Input to change the LIN PHY function mode
`txd`	Data input signal, giving the drive state intended at the LIN pin in LIN PHY transmit mode
`txd_en`	Input signal to mask the `txd` signal. When `txd_en` is "L", the transmitter is controlled so that the `txd` input is ignored and the LIN pin becomes "recessive" (weak pull-up).
`sl_round`	Input configuration signal to tune the falling slew rate of LIN waveform. When the rounding mode is selected, the falling slope of the LIN bus waveform will be more moderate for lower EMI emission.

LIN PHY output pins


Pin	Description
`Lin`	Input/output pin for LIN PHY transceiver. The block's transmitter can drive this pin. The receiver uses it as an input. This pin requires a positive/negative tolerance from −27 V to 42 V (to account for a "lost ground" mode that can give negative inputs, and battery surge cases for the high positive voltages).
`rxd`	Output of the LIN PHY receiver. The voltage level of this signal is V _CCD and reflects the state of the LIN pin.

Operating conditions

Table 5

and

Table 6

show the LIN PHY absolute maximum ratings and operating conditions. See

PSOC™ 4 HV PA datasheet

for more information.

Table 5.
LIN PHY absolute maximum ratings
Parameter	Description	Min.	Typ.	Max.	Units	Details/conditions
V _LIN	LIN pin voltage	−27	–	42	V
I _LIN	LIN pin current	–	–	200	mA
t _SCLIN	Short circuit tolerance: LIN	–	–	60	min	V _BAT = LIN: 3.6 V to 28 V
t _SCLIN	Short circuit tolerance: LIN	–	–	500	ms	V _BAT = LIN: 28 V to 42 V

Table 6.
LIN PHY operating conditions
Parameter	Description	Min.	Typ.	Max.	Units	Details/conditions
V _{BAT_LIN}	V _BAT range for LIN communications	7	–	28	V	LIN2.2 A parameter 10
V _LIN	LIN output voltage	6	–	28	V
R _LIN,PU	LIN pull-up resistor	20	30	47	kΩ
I _{BUS_LIM}	LIN output current	40	–	200	mA	Param 12
V _BUSdom	Receiver dominant state	–	–	0.4	V _BAT	Param 17
V _BUSrec	Receiver recessive state	0.6	–	–	V _BAT	Param 18
V _BUScnt	Receiver center voltage	0.475	0.5	0.525	V _BAT	Param 19
V _BUShys	Receiver hysteresis	–	–	0.175	V _BAT	Param 20
V _OH	Bus transmitter recessive output voltage	V _BAT -2	–	V _BAT	V	Not a LIN 2.2 A specification
V _OL	Bus transmitter dominant output voltage ( V _BAT = V _BUS =7 V)	–	–	1.2	V	RL = 500 Ω (IOL<12 mA)
V _OL	Bus transmitter dominant output voltage ( V _BAT = V _BUS =18 V)	–	–	2	V	RL = 500 Ω (IOL<32 mA)
V _SerDiode	Voltage drop at external series Diodes	0.4	0.7	1	V	Param 21
R _LIN,PU	Internal slave pull-up Resistor	20	30	47	kΩ	Param 26 (RSLAVE)
R _LIN,PD	Internal pull-down resistor for Diagnosis	20	30	47	kΩ	Not a LIN 2.2 A specification

LIN physical layer specification overview

LIN is a low-cost serial communication protocol, which has been standardized by the LIN consortium. The main properties of LIN are:

Single master with one or more slaves
Speeds up to 20 kbps
Single-wire implementation
Low cost silicon implementation based on common UART/SCI interface hardware or equivalent software/hardware state machine

The physical interface is a single-wire (not including ground) using a physical layer interface (PHY). The LIN PHY has two states: the recessive state where the LIN bus is pulled up close to the vehicle battery voltage (a reverse protection diode causes a small voltage drop) and a dominant state, which is essentially 0 V.

Figure 5

shows an overview of a LIN network.

Each node on the LIN network uses a LIN PHY (transceiver) to communicate over the network. The LIN physical layer is independent of the higher LIN protocol layers including master and slave operation. There are no differences between master and slave transceivers. Each LIN network can have up to 16 nodes. The PHY has a transmitter section, which includes the open-drain pull-down transistor and gate driver circuitry, a receiver, and a small pull-up resistor.

The master node includes a termination resistor that ranges from 500 to 1000 Ω depending on network speed and bus length (up to 40 m). The LIN PHY specification specifies network loads of 1000 Ω pull-up with 1 nF bus load capacitance, 680 Ω with 6.8 nF, and 500 Ω with 10 nF. All nodes include a nominal 30 kΩ nominal pull-up resistor; this is intended to compensate for increasing node capacitance (typically ~270 pF/node) to maintain approximately the same pull-up resistor to load capacitance (R × C) time constant as nodes are added. Typically used network speeds are either 10 kbps or 20 kbps.

HVSS firmware configuration

Infineon provides the sample driver library (SDL) including startup code as sample firmware. The SDL provides a simple interface to access various peripherals and is used for system validation, hardware bring-up, benchmarks, feasibility studies, and demos. The SDL integrates device header files, startup code, and peripheral drivers. The SDL contains a set of firmware drivers that provide APIs for accessing device-specific resources and example for each peripheral. See AN230264 - Getting started with PSOC™ 4 HV PA family

[1]

for detailed SDL information.

The SDL should not be used for production purposes because it is not qualified with any automotive standards.

The following sections explain the details of the API and code examples for HVSS.

Peripheral drivers

Peripheral drivers are a set of firmware drivers that provide APIs for accessing the hardware. These APIs perform initialization and control activities of each peripheral.

Table 7

lists and describes the interface to each HVSS function. The peripheral drivers of HVSS are located in the following SDL path:

C:/<user path>\PSoC_Sample_Driver_Library_x.x.x\psoc4hvXXXk\src\drivers\hvss

See

API details

for more information.

Table 7.
HVSS functions
Function	Description
`cy_hvss.c`
`Cy_Hvss_Init`	Configures the HVSS module, which includes RDIV (resistor attenuation) and LIN-PHY configuration. This function should be called before using the LIN communication functions.
`Cy_Hvss_DeInit`	De-initializes both the LIN module and the RDIV
`cy_hvss.h`
`Cy_Hvss_Hvreg_GetStatus`	Gets the status of the HVSS regulator
`Cy_Hvss_Rvid_EnableVS0`	Enables VS0 in resistor attenuator control (RDIV)
`Cy_Hvss_Rvid_DisableVS0`	Disables VS0 in RDIV
`Cy_Hvss_Rvid_EnableVS1`	Enables VS1 in RDIV
`Cy_Hvss_Rvid_DisableVS1`	Disables VS1 in resistor attenuator control (RDIV)
`Cy_Hvss_Rvid_SetPowerMode`	Sets the power domain mode in RDIV
`Cy_Hvss_Rvid_GetPowerMode`	Gets the power domain mode of RDIV
`Cy_Hvss_Rvid_SetAttenuationVS0`	Gets VS0 attenuation of RDIV
`Cy_Hvss_Rvid_GetAttenuationVS0`	Gets VS0 attenuation of RDIV
`Cy_Hvss_Rvid_SetAttenuationVS1`	Gets VS1 attenuation of RDIV
`Cy_Hvss_Rvid_GetAttenuationVS1`	Gets VS1 attenuation of RDIV
`Cy_Hvss_LinPhy_SetRxdPin`	Sets the status of the LIN-PHY RxD pin
`Cy_Hvss_LinPhy_GetRxdPin`	Gets the status of the LIN-PHY; this will give the current status of the LIN RxD pin
`Cy_Hvss_LinPhy_EnableWakeupTimer`	Enables the LIN-PHY wake-up timer; required LIN compatibility in DS mode.
`Cy_Hvss_LinPhy_DisableWakeupTimer`	Disables the LIN-PHY wake-up timer
`Cy_Hvss_LinPhy_GetWakeupTimerStatus`	Gets the status of the LIN-PHY wakeup timer; will give the timer count if running
`Cy_Hvss_LinPhy_EnableFaultTimer`	Enables the LIN-PHY fault timer; required LIN compatibility in DS mode
`Cy_Hvss_LinPhy_DisableFaultTimer`	Disables the LIN-PHY fault timer
`Cy_Hvss_LinPhy_GetFaultTimerStatus`	Gets the status of the LIN-PHY fault timer; will give the timer count if running.
`Cy_Hvss_LinPhy_SetPhyMode`	Sets the LIN-PHY mode
`Cy_Hvss_LinPhy_GetPhyMode`	Gets the current LIN-PHY mode
`Cy_Hvss_LinPhy_SetPhySlRound`	Sets the SL round value of the LIN-PHY for lower EMI
`Cy_Hvss_LinPhy_GetPhySlRound`	Gets the SL round mode of the LIN-PHY
`Cy_Hvss_LinPhy_SetPhyInterface`	Sets the internal or GPIO connection of the LIN-PHY through the HSIOM
`Cy_Hvss_LinPhy_GetPhyInterface`	Gets the connection interface of the LIN-PHY through internal or GPIO
`Cy_Hvss_LinPhy_EnablePhy`	Enables the LIN-PHY
`Cy_Hvss_LinPhy_DisablePhy`	Disables the LIN-PHY
`Cy_Hvss_LinPhy_GetPhyStatus`	Gets the LIN-PHY status: 1- enabled 0 - reset (RxD pin is High-Z)
`Cy_Hvss_LinPhy_ClearInterrupt`	Clears the interrupt from the LIN_INTR register
`Cy_Hvss_LinPhy_SetInterrupt`	Sets the interrupt in the LIN_INTR register
`Cy_Hvss_LinPhy_GetInterruptMask`	Returns the interrupt mask from the LIN_INTR_MASK register
`Cy_Hvss_LinPhy_SetInterruptMask`	Sets the interrupt mask in the LIN_INTR_MASK register
`Cy_Hvss_LinPhy_GetInterruptStatusMasked`	Returns the masked status from the LIN_INTR_MASKED register
`Cy_Hvss_LinPhy_SetWakeupInterruptMask`	Sets the wakeup interrupt status masked the in LIN_INTR_MASK register
`Cy_Hvss_LinPhy_ClearWakeupInterruptMask`	Clears the wakeup interrupt status masked in the LIN_INTR_MASK register
`Cy_Hvss_LinPhy_SetFaultInterruptMask`	Sets the fault interrupt status masked in the LIN_INTR_MASK register
`Cy_Hvss_LinPhy_ClearFaultInterruptMask`	Clears the fault interrupt status masked in the LIN_INTR_MASK register

Startup/initialization sequence

Figure 6

shows the flowchart for HVSS settings.

The

Table 8

and

Table 10

steps are recommended when using HVSS:

Table 8.
HVSS initialization steps
Step number	Step	Description	Values
1	RDIV enable	Enable the resistor dividers of the vsense and vdiag inputs.	Block: VDIVIDER Pin name: `rdiv_en<1:0>` Function: `Cy_Hvss_Rvid_EnableVSx`
2	RDIV active enable	Select power modes where RDIV is enabled: 0=Enable in Active and Deep-Sleep modes 1=Enable in Active mode only	Block: VDIVIDER Pin name: none Function: `Cy_Hvss_Rvid_SetPowerMode`
3	RDIV scale enable	Set the voltage attenuator ratio to either 1/16 or 1/24: 0=16X attenuation 1=24X attenuation	Block: VDIVIDER Pin name: `rdiv_scale<1:0>` Function: `Cy_Hvss_Rvid_SetAttenuationVSx`
4	LIN mode set	Change the LIN PHY function mode (See Table 9 )	Block: LIN PHY Pin name: `lin_mode<2:0>` Function: `Cy_Hvss_LinPhy_SetPhyMode`
5	LIN EMI value set	Set the SL round value of the LIN-PHY for lower EMI: 0=Normal 1=More moderate (rounded) for lower EMI	Block: LIN PHY Pin name: `rdiv_scale<1:0>` Function: `Cy_Hvss_LinPhy_SetPhySlRound`
6	LIN PHY interface set	Set the internal or GPIO connection of the LIN-PHY through the HSIOM: 0= Primary interface (connected to the internal LIN controller through HSIOM) 1= Alternate interface (connected to GPIOs through HSIOM)	Block: LIN PHY Pin name: none Function: `Cy_Hvss_LinPhy_SetPhyInterface`
7	LIN enable	Enable the `LIN-PHY` . enable function: `Cy_Hvss_LinPhy_EnablePhy` disable function: `Cy_Hvss_LinPhy_DisablePhy`	Block: LIN PHY Pin name: `txd_en` Function: `Cy_Hvss_LinPhy_EnablePhy` or `Cy_Hvss_LinPhy_DisablePhy`
8	LIN wakeup timer enable (if applicable)	a. Enable the `LIN-PHY` wake-up timer b. Set the value of the `LIN-PHY` wake-up timer (Number of `LF_CLK` edges before wakeup interrupt is triggered)	Block: LIN PHY Pin name: none Function: `Cy_Hvss_LinPhy_EnableWakeupTimer`
9	LIN fault timer enable (if applicable)	a. Enable the `LIN-PHY` fault timer. b. Set the value of the `LIN-PHY` fault timer (number of `LF_CLK` edges before a fault interrupt is triggered)	Block: LIN PHY Pin name: none Function: `Cy_Hvss_LinPhy_EnableFaultTimer`

Table 9.
LIN PHY function mode
Input				Output (driver)
State No.	LIN transceiver function	LIN_MODE[2:0]	Receiver	Slew control	Slew rate setting	txd = 1	txd = 0	Pull-up
0	Disable	000	Off	No	-	High-Z	High-Z	Off
1	Sleep	001	On (Low power)	No	-	Recessive	Recessive	On
2	Standby	010	On	No	-	Recessive	Recessive	On
3	Diagnosis	011	On	No	-	Recessive	Low (weak)	On/Off
4	Normal mode	100	On	Yes	1.0 V/µs	Recessive	Low (dominant)	On
5		101	On	Yes	1.5 V/µs	Recessive	Low (dominant)	On
6		110	On	Yes	2.0 V/µs	Recessive	Low (dominant)	On
7	Fast mode	111	On	No	-	Recessive	Low (dominant)	On

Table 10.
HVSS deinitialization steps
	Step	Description
1	RDIV control register to default	Set all bits of register to 0 "RDIV enable", "RDIV active enable" and "RDIV scale enable"
2	LIN PHY control register to default	Set all bits of register to 0 "LIN enable", "LIN PHY interface", "SL round" and "LIN mode"
3	LIN PHY timers to default	Set all bits of register to 0 "Wakeup timer" and "Fault timer"
4	LIN interrupt request register to default	Set all bits of register to 0 "Wakeup interrupt" and "Fault interrupt"
5	LIN interrupt set register to default	Set all bits of register to 0 "Wakeup interrupt" and "Fault interrupt"
6	LIN interrupt mask register to default	Set all bits of register to 0 "Wakeup interrupt" and "Fault interrupt"

Selecting the external components

HVREG

Schematic example

Figure 7

shows an example HVREG schematic;

Table 11

shows an example of external components.

Table 11.
HVREG external component example
Symbol	Overview	Parameter
Symbol	Overview	Value 1	Value 2	Remark
C4	Decoupling/smoothing capacitor for the high-voltage domain	2.2 μF X7R	> 50 V
C5	Decoupling capacitor for the high-voltage domain	0.1 μF X7R	> 50 V
C6	Capacitor for the external noise filter	47 pF C0G	> 50 V
C11	Decoupling capacitor for the VDDA domain	0.15 μF X7R	> 6.3 V
C12	Decoupling capacitor for the VDDD domain	0.15 μF X7R	> 6.3 V
C13	Decoupling/smoothing capacitor for the VDDD domain	3.3 μF X7R	> 6.3 V
C18	Decoupling capacitor for the VCCD domain	0.15 μF X7R	> 6.3 V
C21	Reference capacitor for the VREF domain	0.47 μF X7R	> 6.3 V
R2	Input filter resistor for the high-voltage domain	Typ 15 Ω (7.5~15 Ω)	> 0.25 W

Layout example

Figure 8

shows an example of the HVREG layout.

Follow these guidelines for the PCB power supply circuit on the PSOC™ 4 HV PA device:

Place the V_BAT input capacitors C4, C5, and C6 as close as possible to the V_BAT pin. Place C6 closer to the V_BAT pin, followed by C5 and C4. Place the R2 resistor for the input filter next to C4 and draw the layout as linear as possible. If the board has a GND plane, provide a through hole (via) near this capacitor
Place the V_DDA capacitor (C11) as close as possible to the V_DDA pin and the V_SSA pin to minimize the current loop from V_DDA to V_SSA. If the board has a GND plane, provide a through hole near the V_SSA pin of this capacitor
Place the V_DDD capacitors (C12 and C13) as close as possible to the V_DDD pin to minimize the current loop from V_DDD to V_SSD. Place C12 closest to V_DDD, followed by C13. If the board has a GND plane, provide a through hole connecting to the GND plane, near this capacitor
Place the V_CCD capacitor (C18) as close as possible to the V_CCD pin to minimize the current loop from V_CCD to V_SSD. If the board has a GND plane, provide a through hole connecting to the GND plane, near this capacitor
Place the reference voltage capacitor (C21) as close as possible to the V_REFH and V_REFL terminals. It is recommended to place the V_REFH and V_REFL traces diagonally, so that they have the same length. Place this capacitor on the same PCB layer as the device and avoid using through holes
- Provide a through hole for GND plane connection near each GND pin (V_SSD,V_SSA,V_SSL)
- When using LIN, place the LIN capacitor near the LIN and V_SSL pins
Provide a GND plane on the mounting surface of this IC. To effectively dissipate the heat from the QFN-32 package, it is recommended to provide a thermal via in the footprint of the thermal pad

See

AN230370

for schematic and layout examples of each sensor input (current/voltage/temperature).

VDIVIDER

Schematic example

Figure 9

shows an example of the VDIVIDER schematic;

Table 12

shows an example of external components.

Figure 9.
Schematic example of voltage sensor line

Table 12.
VDIVIDER external component example
Symbol	Overview	Parameter
Symbol	Overview	Value 1	Value 2	Remark
R5, R7	Resistor for the external noise filter	2.2 kΩ	> 1/10 W
D3, D4	Transient voltage suppressor (TVS)	Bidirectional	Clamping voltage 44 V	Optional
C9, C19	Capacitor for the external noise filter	3.3 nF X7R	> 50 V
C10, C20	Capacitor for the external noise filter	47 pF C0G	> 50 V

Note:

Resistor values for the voltage path (R5/R7): Note that any deviation from the nominal 2.2 kΩ is associated with a reduction in accuracy.

Layout example

Figure 10

shows an example of the LIN layout.

Follow these guidelines for the design of the voltage sensor line circuit on the PSOC™ 4 HV PA device:

Keep the wiring lengths of VSENSE and VDIAG as equal as possible
Wire the VSENSE and VDIAG sensor lines from each VBAT point
Keep the wiring width in the range of 0.127 mm to the IC terminal width
Guard the entire pattern by GND
Place the GND layer under the sensor line

LIN PHY

Schematic example

Figure 11

shows an example of LIN schematic;

Table 13

shows an example of external components.

Table 13.
LIN external components
Symbol	Overview	Parameter
Symbol	Overview	Value 1	Value 2	Remark
C25	Decoupling capacitor for the LIN domain	220 pF C0G	> 50 V
R16	Input filter resistance for the high-voltage domain	50 mΩ	> 1/3 W
D7	Transient voltage suppressor (TVS) diode	Bidirectional	Clamping voltage 44 V

Layout example

Figure 12

shows an example of the LIN layout.

Follow these guidelines for the PCB HVSS circuit:

Place capacitor (C25) near the LIN and VSSL terminals
Place the TVS diode (D7) for ESD protection near the LIN connector
Connect the LIN wiring as straight as possible
Change the optional filter element (R16) per your application
Place GND vias near the C25 and D7 terminals
Do not connect VSSL to the EP pad
Place a guard under the LIN wiring with a GND layer
Place a guard around LIN with GND

ESD protection

Electro-static discharge (ESD) events generate high voltages and high currents depending on the path the charge takes to go to ground. If not properly bypassed, the voltages cause immediate oxide dielectric breakdown, especially in advanced geometry technologies with thin gate oxides, creating a weak spot in the oxide which allows the current flow and localized heating.

Depending on the current flow, this could cause permanent damage. A high current flow can cause overheating and melt the silicon, which results in creating a permanent short or high-leakage sites. High currents can also cause junction or metal failure. In summary, ESD failures can be caused by oxide breakdown, junction burnout, or metallization failure.

The following sections describe the ESD protection mechanism for each HVSS block.

HVREG protection

Figure 13

shows the detailed block diagram for HVREG ESD protection. HVREG includes the cascode ESD transistors and two pads for the VBAT pin. The cascode ESD transistors are used to bypass the charge to the ground. Two pads for the VBAT pin reduce the impact by oxide breakdown, junction burnout, or metallization failure due to excess current.

VDIVIDER protection

Figure 14

shows the detailed block diagram for VDIVIDER ESD protection.

VDIVIDER includes the cascode ESD transistors for

_SENSE

and

_DIAG

pins, which are used to bypass the charge to ground. The external 2.2 kΩ resistors in series with the voltage sources limit the current during ESD and transient voltage events.

LIN PHY protection

Figure 15

shows the detailed block diagram for LIN PHY ESD protection.

LIN PHY includes an HVPMOS diode, cascode ESD transistors, and two pads for the LIN and VSSL pins. The cascode ESD transistors are used to bypass the charge to VSSL. The two pads for the LIN and VSSL pins reduce the impact by oxide breakdown, junction burnout, or metallization failure due to excess current.

ESD events in an uncontrolled environment

Despite the protection element inside the silicon, ESD events in an uncontrolled environment (end-user, retail customer, etc.) can be much more damaging. System design must take ESD protection on the PCB into account to prevent ESD events in the uncontrolled environment. This is usually done through techniques such as ESD protection devices (external devices), PCB layout techniques that attempt to control ESD, and appropriate grounding and shielding techniques.

PSOC™ 4 HV PA requires sufficient protection to withstand high voltage ESD on specific pins. ESD on LIN,

_BAT

_SENSE

, and

_DIAG

pins is rated at ±8 kV, and is required to be protected by external devices as shown in

Figure 16

API details

This chapter describes the APIs in shown

Table 7

. See the

SDL_psoc4hvpaXXXk.chm

file in the

SDL

path below for more information of all PSOC™ 4 HV PA APIs:

C:/<user path>\ PSoC_Sample_Driver_Library_x.x.x\docs

Cy_Hvss_Init()

cy_en_hvss_status_t Cy_Hvss_Init(cy_stc_hvss_config_t *config)

Description:

This function configures the HVSS module, which includes RDIV (resistor attenuation) and LIN-PHY configuration. This function should be called before using LIN communication functions.

Parameters:

config \ref cy_stc_hvss_config_t

Returns:

CY_HVSS_SUCCESS

– HVSS configuration completed successfully

CY_HVSS_BAD_PARAM

– One or more invalid parameters

CY_HVSS_ERROR

– Error occurred while configuring

Cy_Hvss_DeInit()

cy_en_hvss_status_t Cy_Hvss_DeInit(void)

Description:

This function deinitializes both the LIN module and the RDIV.

Parameters:

None.

Returns:

CY_HVSS_SUCCESS

– HVSS configuration completed successfully

CY_HVSS_BAD_PARAM

– One or more invalid parameters

CY_HVSS_ERROR

– Error occurred while configuring

Cy_Hvss_Hvreg_GetStatus()

__STATIC_INLINE uint8_t Cy_Hvss_Hvreg_GetStatus(void)

Description:

This function gets the status of the HVSS regulator.

Parameters:

None.

Returns:

PWR_GOOD

– Status bit.

Cy_Hvss_Rvid_EnableVS0()

__STATIC_INLINE void Cy_Hvss_Rvid_EnableVS0(void)

Description:

This function enables VS0 in RDIV.

Parameters:

None.

Returns:

None.

Cy_Hvss_Rvid_DisableVS0()

__STATIC_INLINE void Cy_Hvss_Rvid_DisableVS0(void)

Description:

This function disables VS0 in resistor attenuator control (RDIV).

Parameters:

None.

Returns:

None.

Cy_Hvss_Rvid_EnableVS1()

__STATIC_INLINE void Cy_Hvss_Rvid_EnableVS1(void)

Description:

This function enables VS1 in resistor attenuator control (RDIV).

Parameters:

None.

Returns:

None.

Cy_Hvss_Rvid_DisableVS1()

__STATIC_INLINE void Cy_Hvss_Rvid_DisableVS1(void)

Description:

This function disables VS1 in resistor attenuator control (RDIV).

Parameters:

None.

Returns:

None.

Cy_Hvss_Rvid_SetPowerMode ()

__STATIC_INLINE void Cy_Hvss_Rvid_SetPowerMode(cy_en_hvss_rdiv_power_mode_type_t mode)

Description:

This function sets the power domain mode in resistor attenuator control (RDIV).

Parameters:

mode \ref cy_en_hvss_rdiv_power_mode_type_t
- CY_HVSS_RDIV_MODE_ACTIVE_DEEPSLEEP              = 0
- CY_HVSS_RDIV_MODE_ACTIVE_ONLY                   = 1

Returns:

None.

Cy_Hvss_Rvid_GetPowerMode

__STATIC_INLINE cy_en_hvss_rdiv_power_mode_type_t Cy_Hvss_Rvid_GetPowerMode(void)

Description:

This function gets then power domain mode of resistor attenuator control (RDIV).

Parameters:

None.

Returns:

\ref cy_en_hvss_rdiv_power_mode_type_t
- CY_HVSS_RDIV_MODE_ACTIVE_DEEPSLEEP              = 0
- CY_HVSS_RDIV_MODE_ACTIVE_ONLY                   = 1

Cy_Hvss_Rvid_SetAttenuationVS0

__STATIC_INLINE void Cy_Hvss_Rvid_SetAttenuationVS0(cy_en_hvss_rdiv_attenuation_type_t attenuation)

Description:

This function gets the VS0 attenuation of resistor attenuator control (RDIV).

Parameters:

mode \ref cy_en_hvss_rdiv_attenuation_type_t
- CY_HVSS_RDIV_ATTENUATION_16X               = 0
- CY_HVSS_RDIV_ATTENUATION_24X               = 1

Returns:

None.

Cy_Hvss_Rvid_GetAttenuationVS0

__STATIC_INLINE cy_en_hvss_rdiv_attenuation_type_t Cy_Hvss_Rvid_GetAttenuationVS0(void)

Description:

This function gets the VS0 attenuation of resistor attenuator control (RDIV).

Parameters:

None.

Returns:

\ref cy_en_hvss_rdiv_attenuation_type_t
- CY_HVSS_RDIV_ATTENUATION_16X               = 0
- CY_HVSS_RDIV_ATTENUATION_24X               = 1

Cy_Hvss_Rvid_SetAttenuationVS1

__STATIC_INLINE void Cy_Hvss_Rvid_SetAttenuationVS1(cy_en_hvss_rdiv_attenuation_type_t attenuation)

Description:

This function gets the VS1 attenuation of resistor attenuator control (RDIV).

Parameters:

mode \ref cy_en_hvss_rdiv_attenuation_type_t
- CY_HVSS_RDIV_ATTENUATION_16X               = 0
- CY_HVSS_RDIV_ATTENUATION_24X               = 1

Returns:

None.

Cy_Hvss_Rvid_GetAttenuationVS1

__STATIC_INLINE cy_en_hvss_rdiv_attenuation_type_t Cy_Hvss_Rvid_GetAttenuationVS1(void)

Description:

This function gets the VS1 attenuation of resistor attenuator control (RDIV).

Parameters:

None.

Returns:

\ref cy_en_hvss_rdiv_attenuation_type_t
- CY_HVSS_RDIV_ATTENUATION_16X               = 0
- CY_HVSS_RDIV_ATTENUATION_24X               = 1

Cy_Hvss_LinPhy_SetRxdPin

__STATIC_INLINE void Cy_Hvss_LinPhy_SetRxdPin(uint8_t status)

Description:

This function sets the status of the LIN-PHY RxD pin.

Parameters:

status lin

– RxD pin status (HIGH or LOW).

Returns:

None.

Cy_Hvss_LinPhy_GetRxdPin

__STATIC_INLINE uint8_t Cy_Hvss_LinPhy_GetRxdPin(void)

Description:

This function gets the status of the LIN-PHY, which indicates the current status of the LIN RxD pin.

Parameters:

None.

Returns:

uint8_t

– Status of the LIN-PHY.

Cy_Hvss_LinPhy_EnableWakeupTimer

__STATIC_INLINE void Cy_Hvss_LinPhy_EnableWakeupTimer(void)

Description:

This function enables the LIN-PHY wake-up timer, which is required in DS mode for LIN compatibility.

Parameters:

None.

Returns:

None.

Cy_Hvss_LinPhy_DisableWakeupTimer

__STATIC_INLINE void Cy_Hvss_LinPhy_DisableWakeupTimer(void)

Description:

This function disables the LIN-PHY wake-up timer.

Parameters:

None.

Returns:

None.

Cy_Hvss_LinPhy_GetWakeupTimerStatus

__STATIC_INLINE uint16_t Cy_Hvss_LinPhy_GetWakeupTimerStatus(void)

Description:

This function gets the status of the LIN-PHY wakeup timer, which indicates the timer count if running.

Parameters:

None.

Returns:

uint16_t

– Status of the LIN-PHY wakeup timer.

Cy_Hvss_LinPhy_EnableFaultTimer

__STATIC_INLINE void Cy_Hvss_LinPhy_EnableFaultTimer(void)

Description:

This function enables the LIN-PHY fault timer, which is required LIN for compatibility in DS mode.

Parameters:

None.

Returns:

None.

Cy_Hvss_LinPhy_DisableFaultTimer

__STATIC_INLINE void Cy_Hvss_LinPhy_DisableFaultTimer(void)

Description:

This function disables the LIN-PHY fault timer.

Parameters:

None.

Returns:

None.

Cy_Hvss_LinPhy_GetFaultTimerStatus

__STATIC_INLINE uint16_t Cy_Hvss_LinPhy_GetFaultTimerStatus(void)

Description:

This function gets the status of the LIN-PHY fault timer, which provides the timer count if running.

Parameters:

None.

Returns:

uint16_t

– Status of the LIN-PHY fault timer.

Cy_Hvss_LinPhy_SetPhyMode

__STATIC_INLINE void Cy_Hvss_LinPhy_SetPhyMode(cy_en_hvss_lin_phy_mode_type_t mode)

Description:

This function sets the mode of the LIN-PHY.

Parameters:

mode /ref cy_en_hvss_lin_phy_mode_type_t
- CY_HVSS_LIN_PHY_MODE_DISABLED           = 0
- CY_HVSS_LIN_PHY_MODE_SLEEP              = 1
- CY_HVSS_LIN_PHY_MODE_STANDBY            = 2
- CY_HVSS_LIN_PHY_MODE_DIAGNOSIS          = 3
- CY_HVSS_LIN_PHY_MODE_NORMAL_1_0         = 4
- CY_HVSS_LIN_PHY_MODE_NORMAL_1_5         = 5
- CY_HVSS_LIN_PHY_MODE_NORMAL_2_0         = 6
- CY_HVSS_LIN_PHY_MODE_FAST               = 7

Returns:

None

Cy_Hvss_LinPhy_GetPhyMode

__STATIC_INLINE cy_en_hvss_lin_phy_mode_type_t Cy_Hvss_LinPhy_GetPhyMode(void)

Description:

This function gets the current mode of the LIN-PHY.

Parameters:

None.

Returns:

/ref cy_en_hvss_lin_phy_mode_type_t
- CY_HVSS_LIN_PHY_MODE_DISABLED           = 0
- CY_HVSS_LIN_PHY_MODE_SLEEP              = 1
- CY_HVSS_LIN_PHY_MODE_STANDBY            = 2
- CY_HVSS_LIN_PHY_MODE_DIAGNOSIS          = 3
- CY_HVSS_LIN_PHY_MODE_NORMAL_1_0         = 4
- CY_HVSS_LIN_PHY_MODE_NORMAL_1_5         = 5
- CY_HVSS_LIN_PHY_MODE_NORMAL_2_0         = 6
- CY_HVSS_LIN_PHY_MODE_FAST               = 7

Cy_Hvss_LinPhy_SetPhySlRound

__STATIC_INLINE void Cy_Hvss_LinPhy_SetPhySlRound(cy_en_hvss_lin_phy_emi_type_t mode)

Description:

This function sets the SL round value of the LIN-PHY for lower EMI.

Parameters:

mode /ref cy_en_hvss_LinPhy_emi_type_t
- CY_HVSS_LIN_PHY_SL_ROUND_NORMAL                = 0
- CY_HVSS_LIN_PHY_SL_ROUND_MODERATE              = 1

Returns:

None.

Cy_Hvss_LinPhy_GetPhySlRound

__STATIC_INLINE cy_en_hvss_lin_phy_emi_type_t Cy_Hvss_LinPhy_GetPhySlRound(void)

Description:

This function gets the SL round mode of the LIN-PHY.

Parameters:

None.

Returns:

/ref cy_en_hvss_LinPhy_emi_type_t
- CY_HVSS_LIN_PHY_SL_ROUND_NORMAL                = 0
- CY_HVSS_LIN_PHY_SL_ROUND_MODERATE              = 1

Cy_Hvss_LinPhy_SetPhyInterface

__STATIC_INLINE void Cy_Hvss_LinPhy_SetPhyInterface(cy_en_hvss_lin_phy_interface_type_t mode)

Description:

This function sets the internal or GPIO connection of the LIN-PHY through the HSIOM.

Parameters:

/ref cy_en_hvss_LinPhy_interface_type_t
- CY_HVSS_LIN_PHY_INTERFACE_PRIMARY         = 0
- CY_HVSS_LIN_PHY_INTERFACE_SECONDARY       = 1

Returns:

None.

Cy_Hvss_LinPhy_GetPhyInterface

__STATIC_INLINE cy_en_hvss_lin_phy_interface_type_t Cy_Hvss_LinPhy_GetPhyInterface(void)

Description:

This function gets the connection interface of the LIN-PHY through internal or GPIO.

Parameters:

None.

Returns:

/ref cy_en_hvss_LinPhy_interface_type_t
- CY_HVSS_LIN_PHY_INTERFACE_PRIMARY         = 0
- CY_HVSS_LIN_PHY_INTERFACE_SECONDARY       = 1

Cy_Hvss_LinPhy_EnablePhy

__STATIC_INLINE void Cy_Hvss_LinPhy_EnablePhy(void)

Description:

This function enables the LIN-PHY.

Parameters:

None.

Returns:

None.

Cy_Hvss_LinPhy_DisablePhy

__STATIC_INLINE void Cy_Hvss_LinPhy_DisablePhy(void)

Description:

This function disables the LIN-PHY.

Parameters:

None.

Returns:

None.

Cy_Hvss_LinPhy_GetPhyStatus

__STATIC_INLINE uint8_t Cy_Hvss_LinPhy_GetPhyStatus(void)

Description:

This function gets the status of the LIN-PHY.

1: Enabled

0: Reset (RxD pin is High-Z)

Parameters:

None.

Returns:

uint8_t

– Status of the LIN-PHY.

Cy_Hvss_LinPhy_ClearInterrupt

__STATIC_INLINE void Cy_Hvss_LinPhy_ClearInterrupt(uint32_t interrupt)

Description:

This function clears the interrupt from the LIN_INTR register.

Parameters:

interrupt – Interrupt mask for the interrupt.

Returns:

None.

Cy_Hvss_LinPhy_SetInterrupt

__STATIC_INLINE void Cy_Hvss_LinPhy_SetInterrupt(uint32_t interrupt)

Description:

This function sets the interrupt in the LIN_INTR register.

Parameters:

interrupt

– Interrupt mask for the interrupt.

Returns:

None.

Cy_Hvss_LinPhy_GetInterruptMask

__STATIC_INLINE uint32_t Cy_Hvss_LinPhy_GetInterruptMask(void)

Description:

This function returns the interrupt mask from the LIN_INTR_MASK register.

Parameters:

None.

Returns:

uint32_t

–Interrupt bit mask.

Cy_Hvss_LinPhy_SetInterruptMask

__STATIC_INLINE void Cy_Hvss_LinPhy_SetInterruptMask(uint32_t interrupt)

Description:

This function sets the interrupt mask in the LIN_INTR_MASK register.

Parameters:

interrupt

– Interrupt mask for the interrupt.

Returns:

None.

Cy_Hvss_LinPhy_GetInterruptStatusMasked

__STATIC_INLINE uint32_t Cy_Hvss_LinPhy_GetInterruptStatusMasked(void)

Description:

This function returns the masked status from the LIN_INTR_MASKED register.

Parameters:

None.

Returns:

Interrupt bit mask(s).

Cy_Hvss_LinPhy_SetWakeupInterruptMask

__STATIC_INLINE void Cy_Hvss_LinPhy_SetWakeupInterruptMask(void)

Description:

This function sets the wakeup interrupt status masked in the LIN_INTR_MASK register.

Parameters:

None.

Returns:

None.

Cy_Hvss_LinPhy_ClearWakeupInterruptMask

__STATIC_INLINE void Cy_Hvss_LinPhy_ClearWakeupInterruptMask(void)

Description:

This function clears the wakeup interrupt status masked in the LIN_INTR_MASK register.

Parameters:

None.

Returns:

None.

Cy_Hvss_LinPhy_SetFaultInterruptMask

__STATIC_INLINE void Cy_Hvss_LinPhy_SetFaultInterruptMask(void)

Description:

This function sets the fault interrupt status masked in the

LIN_INTR_MASK

Parameters:

None.

Returns:

None.

Cy_Hvss_LinPhy_ClearFaultInterruptMask

__STATIC_INLINE void Cy_Hvss_LinPhy_ClearFaultInterruptMask(void)

Description:

This function clears the fault interrupt status masked in the

LIN_INTR_MASK

Parameters:

None.

Returns:

None.

Summary

This application note guides you through the details of the high-voltage subsystem of PSOC™ 4 HV PA, enabling you to connect automotive batteries directly and achieve battery monitoring and management applications with a minimal number of external components. Infineon provides evaluation boards and a wealth of sample software to help you get started with the PSOC™ 4 HV PA family. To access the evaluation board, contact your sales representative or reach out to

Infineon Technical Support

Glossary

Table 14.
Glossary
Terms	Description
A/D converter	analog to digital converter
ADC	analog to digital converter
AHB	advanced high-performance bus
API	application programming interface
BOD	brown-out detectors
CPU	central processing unit
CPUSS	CPU sub-system
DAP	debug access port
DC	direct current
DMA	direct memory access
DMAC	DMA controller
DW	data wire
ECC	error correction code (safety)
ECU	electronic control unit
EM	electro-magnetic
EMI	electro-magnetic interference
ESD	electro-static discharge
GPIO	general purpose I/O
HSIOM	high-speed I/O matrix
HVREG	high-voltage regulator
HVSS	high-voltage subsystem
I/O	input or output
IOSS	I/O subsystem
IRC	interrupt controller
IRQ	interrupt request
ISR	interrupt service routine
LIN	local interconnect network
MCU	microcontroller unit
MPU	memory protection unit
NMI	non-maskable interrupt
PA	precision analog
PACSS	precision analog channel subsystem
PCB	printed circuit board
PG	power good
PHY	physical interface transceiver
POR	power on reset
PWM	pulse width modulation
RAM	random access memory
RDIV	resistor attenuator control
RF	radio frequency
ROM	read-only memory
SCB	serial communication block
SDL	sample driver library
SPI	serial peripheral interface
SRAM	static RAM
SRSS	system resource sub-system
TCPWM	timer, counter and PWM
TRM	technical reference manual
TVS	transient voltage suppressor
VDIVIDER	voltage divider
WDT	watchdog timer

References

The following are the PSOC™ 4 HV PA family series application notes, datasheets and technical reference manuals. Contact

Technical Support

to obtain these documents and sample driver library.

Application notes

AN230264 - Getting started with PSOC™ 4 HV PA family
AN230265 - Hardware design guide for PSOC™ 4 HV PA family
AN230370 - Precision analog channel subsystem in PSOC™ 4 HV PA family

Device datasheet

PSOC™ 4 HV precision analog datasheet

Architecture reference manual

PSOC™ 4 HV PA architecture reference manual (RM)

Registers reference manual

PSOC™ 4 HV PA registers reference manual (RM)

Evaluation board user guide

PSOC™ 4 HV PA evaluation board user guide

Sample driver library (SDL)

PSOC™ 4 HV PA sample driver library

Revision history


Document revision	Date	Description of changes
**	2021-11-22	Initial release
*A	2023-04-19	Template update; no content updated.
*B	2024-11-20	Updated to the latest branding guidelines Sunset review complete

AN230371 High voltage subsystem (HVSS) in PSOC HV PA family

About this document​

Scope and purpose​

Intended audience​

Introduction​

HVSS overview​

HVREG​

Block description​

HVREG input pins​

HVREG output pins​

Operating voltage​

VDIVIDER​

Block description​

VDIVIDER input pins​

VDIVIDER output pins​

Operating voltage​

LIN PHY​

Block description​

LIN PHY input pins​

LIN PHY output pins​

Operating conditions​

LIN physical layer specification overview​

HVSS firmware configuration​

Peripheral drivers​

Startup/initialization sequence​

Selecting the external components​

HVREG​

Schematic example

Layout example

VDIVIDER​

Schematic example

Layout example

LIN PHY​

Schematic example

Layout example

ESD protection​

HVREG protection​

VDIVIDER protection​

LIN PHY protection​

ESD events in an uncontrolled environment​

API details​

Summary​

Glossary​

References​

Revision history​

About this document

Scope and purpose

Intended audience

Introduction

HVSS overview

HVREG

Block description

HVREG input pins

HVREG output pins

Operating voltage

VDIVIDER

Block description

VDIVIDER input pins

VDIVIDER output pins

Operating voltage

LIN PHY

Block description

LIN PHY input pins

LIN PHY output pins

Operating conditions

LIN physical layer specification overview

HVSS firmware configuration

Peripheral drivers

Startup/initialization sequence

Selecting the external components

HVREG

VDIVIDER

LIN PHY

ESD protection

HVREG protection

VDIVIDER protection

LIN PHY protection

ESD events in an uncontrolled environment

API details

Summary

Glossary

References

Revision history